In order to meet the requirements on performance, power, area of floating-point computing in M-DSP, the architecture of a M-DSP, as well as the characteristics of all the instructions related to its floating-point computing were analyzed, and a Floating-point Multiply ACcumulate (FMAC) with high performance and low power was proposed. The proposed FMAC has structure with separated single and double precision path, which was divided into 6-stage pipelines; its key modules including multiplier and shift device were designed for reuse, and the operations including single and double precision floating-point multiplication, multiply-add and multiply-sub, floating-point complex multiplication, dot product, etc. were all implemented in it. The proposed FMAC was fully verified and synthesized by using Design Compiler with 45nm technique of Synopsys Company. Experimental results show that the frequency of the proposed FMAC is up to 1GHz, the area is 36856μm ²; compared with the FMAC of FT-XDSP, the area is saved by 12.95%, and the critical path was shortened by 2.17%.